PA-RISC Processors
PA-RISC processors are based on an HP RISC architecture developed in the 1980s, used in HP Unix servers and workstations until the 2000s. There were many different PA-RISC processor incarnations: early 32-bit PA-RISC 1.0 in the 1980s, modern 32-bit PA-RISC 1.1 in the 1990s RISC era and final 64-bit PA-RISC 2.0 until Itanium in the 2000s.
| CPU | Architecture | Year | FETs | Clock up to |
Cache max |
Bus | Scalar | SMP | Units |
|---|---|---|---|---|---|---|---|---|---|
| FOCUS | FOCUS 32-bit stack |
1982 | 450k NMOS |
18 MHz | 16 KB external |
Custom | 1-way | yes | INT, FPU |
| TS-1 | PA-RISC 1.0 32-bit RISC |
1986 | TTL | 8 MHz | 128 KB external |
Custom | 1-way | INT, FPU | |
| NS-1 | PA-RISC 1.0 32-bit RISC |
1987 | 144k NMOS |
30 MHz | 128 KB external |
SMB | 1-way | INT, FPU | |
| PRISM Apollo |
PRISM 32-bit VLIW |
1988 | 18 MHz | 196 KB external |
X-bus | 3-wide | yes | INT, FPU | |
| NS-2 | PA-RISC 1.0 32-bit RISC |
1989 | 183k NMOS |
27.5 MHz | 1 MB external |
SMB | 1-way | yes | INT, FPU |
| PCX | PA-RISC 1.0 32-bit RISC |
1990 | 196k | 50 MHz | 1 MB external |
SMB | 1-way | yes | INT, FPU |
| PA-7000 | PA-RISC 1.1a 32-bit RISC |
1991 | 577k | 66 MHz | 512 KB external |
PBus | 1-way | INT, FPU | |
| PA-7100 PA-7150 |
PA-RISC 1.1b 32-bit RISC |
1992 | 850k | 125 MHz | 3 MB external |
PBus | 2-way | yes | INT, FP |
| PA-7100LC | PA-RISC 1.1c 32-bit RISC |
1994 | 900k | 100 MHz | 1 KB 2 MB L2 |
GSC | 2-way | 2 INT, FP MIOC, MAX-1 |
|
| PA-7200 | PA-RISC 1.1d 32-bit RISC |
1995 | 1.3M | 140 MHz | 2 KB 3 MB L2 |
Runway | 2-way | yes | 2 INT, FP |
| PA-7300LC | PA-RISC 1.1e 32-bit RISC |
1996 | 9.2M | 180 MHz | 128 KB 8 MB L2 |
GSC | 2-way | 2 INT, FP MIOC, MAX-1 |
|
| PA-8000 | PA-RISC 2.0 64-bit RISC |
1996 | 3.8M | 230 MHz | 2 MB external |
Runway | 4-way | yes | 4 INT, 4 FP 2 L/S, MAX-2 |
| PA-8200 | PA-RISC 2.0 64-bit RISC |
1997 | 4.5M | 300 MHz | 4 MB external |
Runway | 4-way | yes | 4 INT, 4 FP 2 L/S, MAX-2 |
| PA-8500 | PA-RISC 2.0 64-bit RISC |
1998 | 140M | 440 MHz | 1.5 MB on-chip |
Runway | 4-way | yes | 4 INT, 4 FP 2 L/S, MAX-2 |
| PA-8600 | PA-RISC 2.0 64-bit RISC |
2000 | 140M | 550 MHz | 1.5 MB on-chip |
Runway | 4-way | yes | 4 INT, 4 FP 2 L/S, MAX-2 |
| PA-8700 | PA-RISC 2.0 64-bit RISC |
2001 | 186M | 875 MHz | 2.25 MB on-chip |
Runway | 4-way | yes | 4 INT, 4 FP 2 L/S, MAX-2 |
| PA-8800 dual-core |
PA-RISC 2.0 64-bit RISC |
2004 | 300M | 1 GHz | 2×1.5 MB 32 MB L2 |
Itanium 2 | 2×4-way | yes | 4 INT, 4 FP 2 L/S, MAX-2 – 2 cores |
| PA-8900 dual-core |
PA-RISC 2.0 64-bit RISC |
2005 | 317M | 1.1 GHz | 2×1.5 MB 64 MB L2 |
Itanium 2 | 2×4-way | yes | 4 INT, 4 FP 2 L/S, MAX-2 – 2 cores |
| PA-9000 | PA-WideWord 64-bit VLIW |
dropped | Explicitly Parallel Instruction Computing (EPIC) | ||||||
History of PA-RISC
PA-RISC was HP’s RISC architecture, incepted in the 1980s and developed in three versions (PA 1.0, 1.1 and 2.0) in four phases of PA-RISC: Infancy, Growth, Maturity and Decline. Throughout the decades, PA-RISC had strong competition from late CISC and other RISC platforms in the era of technical Unix workstations and business servers.
PA-RISC, the Precision Architecture, was an offspring from HP research and development in the 1980s to replace 16-bit stack-based CPUs in HP 3000 servers and Motorola CPUs in Unix systems with a common, new system architecture, based on new RISC philosophies.
PA-RISC platform and ISA were built from the ground up
by HP engineers in HP R&D and fabrication facilities.
PA-RISC was implemented almost exclusively in HP’s own processors, built in its VLSI Technology Center (VTC) and Systems & VLSI Technology Operation (SVTO) divisions. PA-RISC started with early TTL and NMOS versions in the 1980s and grew to integrated 32-bit and 64-bit RISC processors in the 1990s and 2000s.
PA-RISC processors started as a conservative RISC design in the 1980s that was developed into a major player of the Unix and RISC era. Performance was on par with other RISCs in the early years, but PA-RISC grew into a high-performance RISC platform in the later 1990s, especially with later PA-8000-based CPUs and competed with supercomputers.
Infancy (early PA-RISC)
First PA-RISC processors were designed in the mid-1980s by HP and released in the Infancy (I) phase of PA-RISC. These 32-bit RISC processors implemented PA-RISC 1.0 in multi-chip designs with separate chips for the central processing unit, contrary to the mostly single-chip post-PA-7000 processors from the 1990s.
Early PA-RISC CPUs were based on TTL in the beginning, followed by NMOS-III and finally moved to CMOS26B. HP’s PA-RISC 1.0 designs had clock speeds from 8 MHz up to 50 MHz in later versions, with 128 to 512 MB main memory. System designs were mostly based on HP System Main Bus (SMB) used in early HP 9000 800 servers.
TS-1
TS-1 was the very first PA-RISC production processor from HP, introduced in 1986. It implemented PA-RISC 1.0 on six TTL boards and was used in the first PA-RISC computer shipped by HP, the HP 9000 840. HP moved to NMOS with the next generation CPUs before settling with CMOS later.
NS-1 and NS-2
NS-1 was the first implementation of PA-RISC 1.0 in a new NMOS process, released in 1987 shortly after the original TTL-based TS-1. HP NS-1 PA-RISC processors were used in HP 9000 800 servers of the mid to late-1980s which competed with other early RISC platforms like MIPS and later CISC offerings like VAX and Motorola 68020 and 68030.
NS-2 was the final HP NMOS PA-RISC processor, a tweaked follow-on to the NS-1, introduced in 1989-90. NS-2 increased pipeline stages from three to five, had new TLB and cache controllers and significantly larger caches and TLB. NS-2 was used in late-1980s HP 9000 servers and competed with other early RISC platforms.
PCX (CMOS26B)
PCX was the last PA-RISC 1.0 design, introduced 1990 and the first PA-RISC processor fabricated in a CMOS process. PCX implemented the PA-RISC NS-1/NS-2 design and several of the processor functions previously supplied on external VLSI chips onto a single CPU chip. It was used in several 1990s HP 9000 PA-RISC servers.
Growth (PA-RISC 1.1)
PA-RISC moved to more integrated and advanced processor designs in the early 1990s and extended PA-RISC architecture to version 1.1. One new group of PA-RISC 1.1 processors was developed in the early-1990s Growth phase of PA-RISC: PA-7000 and the more powerful PA-7100 CPU, core components of HP’s entry into the era of RISC workstations.
PA-7000
HP developed the PA-7000 as a PA-RISC processor for ow cost desktop workstation systems
at the beginning of the RISC workstation era in 1991.
Earlier PA-RISC 1.0 processors from the 1980s were mostly geared towards transaction processing and multi-user environments in large and expensive servers.
HP’s design process for the PA-7000 used existing technologies and implemented the first extension to PA-RISC architecture after five years. HP collaborated with Texas Instruments for the PA-7000 floating point unit, a first for HP. PA-7000 leveraged previous PCX PA-RISC design for the computing core, extending it to PA-RISC 1.1.
PA-7100
PA-7100 processors were released a year later, in 1992, and were the foundation of many successful HP 9000 PA-RISC computers in the beginning RISC decade of the 90s. The processing core is close to the PA-7000 but was modified by HP to scale to higher speeds and facilitate superscalarity, allowing the PA-7100 to execute two executions per cycle.
The previously external FPU was redesigned in-house and moved on-chip, taking up about one third of the transistor count. The link between the PA-7100 and its instruction cache was doubled in width compared to the PA-7000.
Maturity (PA-RISC in the 1990s)
During PA-RISC Maturity in the mid-1990s, HP developed final PA-RISC 1.1 and first 64-bit PA-RISC 2.0 processors.
At the height of 32-bit PA-RISC, integrated LC
PA-RISC processors for lower-cost workstations, PA-7100LC and PA-7300LC, and the powerful PA-7200 were produced and widely sold with HP 9000 workstations and servers.
In parallel, HP developed PA-RISC 2.0 during the 1990s, extended its architecture to 64-bit and significantly reworking the PA-RISC processing core with the PA-8000 processor, slightly extended with the follow-on PA-8200, both still conservative PA-RISC processors. The eventual decline of PA-RISC was foreshadowed already by the PA-8500, which broke several HP traditions to keep PA-RISC in the market.
PA-7100LC
PA-7100LC was the first highly-integrated PA-RISC processor, released by HP in 1994.
With a simple 32-bit PA-RISC superscalar core, they integrated memory and I/O controllers onto the chip and made highly-integrated PC-like workstations possible in the mid-1990s.
They carried HP’s high-volume products
for 2½ years.
There was a long gap until 1996, when HP released the follow-on PA-7300LC, another highly integrated CPU with similar product outlook. HP missed the chance to improve production processes or increase clock speed above 100 MHz, loosing the competitive edge in 32-bit RISC computing in the mid-1990s.
PA-7200
HP released PA-7200 processors in 1995 as a high-performance general-purpose CPU for technical computing lineup. PA-7200 followed in the steps of PA-7100 processors and added higher frequency and a new high-bandwidth bus interface to enable specialized applications with large working sets. It was a pretty fast mid-1990s RISC microprocessor.
PA-7200 were expensive to fabricate and were used in only few 32-bit HP Visualize workstations and servers for Unix in the mid-1990s before the 64-bit PA-8000.
PA-7300LC
HP PA-7300LC was another 32-bit integrated PA-RISC processor, released in parallel to HP’s newer 64-bit PA-8000 to revitalize HP’s low-end and midrange systems.
It was based on the PA-7100LC core with large on-chip caches, relatively simple by current standards
to update high-volume products
after 2½ years of PA-7100LC.
Due to the on-chip memory, I/O and cache controllers, PA-7300LC could be used in highly integrated systems that used the same I/O devices as the PA-7100LC, due to the same GSC main bus and system design.
PA-8000 and PA-8200
HP PA-8000 were the first 64-bit RISC processors by HP implementing the new PA-RISC 2.0 architecture. Released in 1996 with a completely redesigned processor design, four-way superscalarity and strong out of order execution capabilities, the PA-8000 CPU core was re-used in all PA-8x00 series processors for almost a decade.
PA-8200 were a mild improvement to the original PA-8000, released in 1997.
PA-8200 was designed to offer improved performace and compatibility with existing applications in a short time to market.
The availability of new 4 Mb SRAMs with faster access times allowed for increased CPU speed and larger (off-chip) caches.
Other high benefit, low risk
improvements include an increase of BHT and TLB.
PA-8500
PA-8500 processors were released a year later in 1998. PA-8500 was functionally very similar to PA-8000 and PA-8200, but added very large on-chip caches to the CPU, an unorthodox choice according to HP tradition. This helped HP to refreshen its RISC lineup in preparation of the long, and eventually delayed transition to Itanium (EPIC).
In the mid to late-1990s, HP looked for external fabs to implement its CPU designs due to technological and performance constraints in its own fabs. HP went to Intel, its partner in developing Itanium. This eventually made huge PA-RISC CPUs with very large on-chip L1 caches possible, breaking a long-standing HP tradition of no L1 on the CPU die but resulting in very high processor performance.
Decline until the 2000s
PA-RISC processors and chipsets for HP 9000 had been designed and fabricated by HP in its own plants and design labs for decades. From the foggy days of TTL and NMOS in the 1980s until the 64-bit PA-8200 processor in 1997, HP produced everything in house: Processors, chipsets and boards were designed and manufactured mainly in Fort Collins (Colorado), Palo Alto, and Cupertino.
Since the mid-90s, HP started to fall behind in CPU manufacturing processes – most chips were one (or more) process generations behind contemporary counterparts from other vendors. This was the result of huge investments other CPU producers poured into fabs and R&D, where HP could not keep up. The outcome was HP not being able to make more aggressive design choices while fabbing processors in its own plants.
PA-8600 and PA-8700
With PA-8700 processors in 2001, HP moved to IBM for fabbing, resulting in the first PA-RISC processor on a Silicon-on-Insulator (SOI) process. The last dual-core PA-8800 and PA-8900 processors were supposedly also fabbed at IBM as the last members of the PA-RISC processor family.
HP PA-8700 was the last conventional PA-RISC 2.0 processor, before the move to dual-core PA-8800 and PA-8900.
Released in 2001, PA-8700 were a stop-gap measure by HP while waiting for Itanium processor to ship – originally planned for 1999.
As MPR put it, HP is developing a processor called the PA-8700 to extend its current RISC line, tiding over customers until Merced systems are available.
PA-8800 and PA-8900
When it became clear in the late-1990s that Itanium Merced processors will be significantly delayed until the early 2000s, HP decided to extend the life of PA-RISC by a few years. The plan by 1998 was to integrate two PA-8x00 64-bit cores onto a single processor with large caches: enter the PA-8800 and PA-8900 CPUs.
With this development, HP had the option to offer powerful PA-RISC processors in parallel to Itanium for four years
to ease transition to the new IA64 architecture.
HP PA-8800 PA-RISC were last of the line of 64-bit PA-RISC processors, released in 2004. Their dual-core integration was the last PA-RISC evolutionary step to increase the performance of the original PA-8000 core. PA-8800 were offered only in some niche mid-2000s PA-RISC systems.
HP PA-8900 PA-RISC were the pinnacle of 64-bit PA-RISC processor design (2005) and improved on the PA-8800 only slightly. No formal SPEC benchmark scores are known and PA-8900 were sold only as a slight upgrade to PA-8800-based 64-bit PA-RISC systems. This way, PA-RISC eked out a few more years on the HP lineup.
PA-RISC to Merced (2000s)
In parallel to its PA-RISC development in the 1990s, HP already started to plan for a transition to a post-RISC phase in the 2000s.
HP had spend many years researching VLIW (EPIC
) processor architectures at the time, and joined forces with Intel to commercialize VLIW for the computing mass market.
HP had planned to move from RISC to a new VLIW (or ILP, instruction level parallelism) processor architecture during the 1990s. The end of PA-RISC was thus set in motion in the mid-1990s, with the expected move to VLIW processors forecasted for the late 1990s. HP had several R&D projects on VLIW, including an architecture extending PA-RISC to ILP called PA-WideWord.
When HP invited Intel into our [HP] lab, we showed them the architecture that will become the pervasive 64-bit architecture of the 21st century.
HP and Intel had big plans for revolutionizing the computing industry since RISC architectures had ran their course, based on their assessments. The resulting Intel-HP VLIW-EPIC architecture was eventually marketed as Itanium by Intel and HP, formally called IA64, and sometimes shortened to IPF, Itanium Processor Family. HP provided large parts of the architecture and research impetus behind Itanium.
The first commercial Itanium processor was Merced, released in 2001 and mostly designed by Intel. Merced was used in very early Itanium workstations and computers that were more prototypes than commercial products. They were rather slow CPUs and late to market, so HP had to bridge the gap with PA-RISC extensions like PA-8800 and PA-8900.
Merced was soon followed by Itanium 2 processors, with more HP influence in CPU design and architecture. McKinley was the first Itanium 2 processor, released in 2002 and used in many HP workstations and servers. McKinley was much faster than the original Itanium Merced and very strong in floating point (FP) – but still late to market when the engineering ecosystem moved to AMD’ 64-bit extension to x86 (x86_64).